Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, such as an electrical charge or voltage, which represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits. The possible bit values that can be stored in an analog memory cell are also referred to as the memory states of the cell.
Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
The analog values read from analog memory cells are sometimes distorted. The distortion may be due to various reasons, such as electrical field coupling from neighboring memory cells, disturb noise caused by memory access operations on other cells in the array and threshold voltage drift caused by device aging. Some common distortion mechanisms are described in the article by Bez et al., cited above. Distortion effects are also described by Lee et al., in “Effects of Floating Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, (23:5), May, 2002, pages 264-266, which is incorporated herein by reference.
Reading data from analog memory cells often involves comparing the analog values stored in the cells to one or more thresholds, or reference levels. Several methods for determining the appropriate threshold values are known in the art. For example, U.S. Pat. No. 5,657,332, whose disclosure is incorporated herein by reference, describes methods for recovering from hard errors in a solid-state memory system. Hard errors may arise from cells whose threshold voltages drifted from their intended level to cause read errors. The memory system includes an array of memory cells, each cell capable of having its threshold voltage programmed or erased to an intended level. An error checking scheme is provided for each of a plurality of groups of cells for identifying read errors therein. A read reference level is adjusted before each read operation on the individual group of cells containing read errors, each time the read reference level being displaced a predetermined step from a reference level for normal read, until the error checking means no longer indicates read errors. The drifted threshold voltage of each cell associated with a read error is re-written to its intended level.
U.S. Pat. No. 7,023,735, whose disclosure is incorporated herein by reference, describes methods for reading Flash memory cells, which, in addition to comparing the threshold voltages of Flash cells to integral reference voltages, compare the threshold voltages to fractional reference voltages.
U.S. Patent Application Publication 2007/0091677, whose disclosure is incorporated herein by reference, describes methods, devices and computer readable code for reading data from one or more flash memory cells, and for recovering from read errors. In some embodiments, in the event of an error correction failure by an error detection and correction module, the flash memory cells are re-read at least once using one or more modified reference voltages, until successful error correction may be carried out. In some embodiments, after successful error correction, a subsequent read request is handled without re-writing data to the flash memory cells in the interim.
U.S. Pat. No. 6,963,505, whose disclosure is incorporated herein by reference, describes a method, circuit and system for determining a reference voltage. In some embodiments a set of operating reference cells is established to be used in operating cells in a Non-Volatile Memory (NVM) block or array. At least a subset of cells of the NVM block or array may be read using each of two or more sets of test reference cells, where each set of test reference cells may generate or otherwise provide reference voltages at least slightly offset from each other set of test reference cells. For each set of test reference cells used to read at least a subset of the NVM block, a read error rate may be calculated or otherwise determined. A set of test reference cells associated with a relatively low read error rate may be selected as the set of operating reference cells to be used in operating other cells, outside the subset of cells, in the NVM block or array.
U.S. Pat. No. 7,196,928 and U.S. patent Application Publications 2006/0221692, 2007/0103986, 2007/0109845 and 2007/0109849, whose disclosures are incorporated herein by reference, describe several processes for reading a memory cell, which take into account the programmed state of an adjacent memory cell.
Some known methods use information regarding the quality of stored data when reading the data from memory cells. For example, U.S. Pat. No. 6,751,766, whose disclosure is incorporated herein by reference, describes several methods for assessing the quality of data stored in a memory system, and for operating the memory system according to the assessed quality. The data quality is sometimes assessed during read operations. Subsequent use of an Error Correction Code (ECC) can utilize the quality indications to detect and reconstruct the data with improved effectiveness. Alternatively, a statistics of data quality can be constructed and digital data values can be associated in a modified manner to prevent data corruption.